As prior art technologies in the field of optical coordinate system input devices to which the present invention belongs, there are many inventions such as U.S. Pat. Nos. 3,764,813; 3,775,560; 3,860,754; 4,122,438; 4,198,623; 4,267,443; 4,301,447; 4,313,109; and 4,384,201.
Among these prior technologies, U.S. Pat. No. 4,243,879 (Arthur B. Carroll et al.) includes an erroneous detection preventive means to improve a problem in a light receptor and minimize erroneous operation of the device.
However, this type of optical coordinate system input device, when employed with manual input often fails to prevent erroneous operations.
One form of the prior art optical coordinate system input device involving various factors of erroneous operations is explained hereunder.
The optical coordinate system input device is attached on the front face of a display plane of a CRT display, LCD (liquid crystal display apparatus), etc., to operate in a scanning mode where respective light receptor elements sequentially receive light signals produced from respective light emitting elements. It is widely used as a coordinate system input device for a personal computer, etc. using a positional input corresponding to the position of a light signal blocked by a finger or other interposed object.
In this type of optical coordinate system input device, LED or other light emitting elements deteriorate and reduce their light emitting amounts in a relatively short time. Insufficient light emission also occurs when dust rests and accumulates on the light emitting elements. Since a decrease in the light emitting amounts inevitably invites a decrease in the light reception level of the light receptor elements, the personal computer, etc. often erroneously recognizes an input when no light signal is blocked on purpose by a finger or other object.
In the prior art technologies, light emitting elements are deemed to be deteriorated when a cursor can not be located on a predetermined position of the display plane of a CRT display or other image display apparatus. However, since an erroneous coordinate input is also caused by an erroneous operation of the personal computer or the CRT display, it is difficult to acknowledge whether the light emitting elements themselves are deteriorated or dusty, or the computer or the CRT display malfunctions. Therefore, a user may often fail to timely cope with deterioration of the light emitting elements, and this invites a serious situation of the computer system where a normal operator cannot effect his subsequent instruction.
In this connection, a recent proposal is the use of an attenuation filter made of an acrylic or other plate having a light transmission of about 50% and interposed between an array of light emitting elements and an array of light receptor elements to judge from the coordinate system input position on the display screen whether the receptor elements receive light signals above a predetermined level or not. Thereby, deterioration or dusty condition of the light emitting elements themselves is determined for subsequent exchange or cleaning thereof.
A second form of the prior art optical coordinate system input device is explained hereinbelow.
The optical coordinate system input device is disposed at the front face of a CRT display, LCD or other image display apparatus and activated to supply a coordinate position input to a computer. A number of pairs of light emitting elements and light receptor elements are opposed to each other along the outer peripheral margins of the screen of the CRT display, etc. so that the light emitting elements and light receptor elements are selectively scanned to detect any interruption of a light signal by a finger or other object during the scanning to obtain a coordinate system signal.
FIG. 11 is a block circuit diagram of the prior art optical coordinate system in which a number of light emitting diodes L1 through Ln are placed on two adjacent margins of the front face outer periphery of a CRT or other image display apparatus. Photo transistors PT1 through PTn employed as the light receptor elements are placed on the other two adjacent. margins and opposed to the light emitting diodes L1 through Ln. Horizontally opposed pairs of light emitting diodes (L1 through Lm) and photo transistors (PT1 through PTm) form X axes of the coordinate system, and vertically opposed pairs of light emitting diodes (Lm+1 through Ln) and photo resistors (PTm+1 through PTn) form Y axes of the coordinate system. Cathodes of the light emitting diodes L1 through Ln and emitters of the photo resistors PT1 through PTn are all connected to ground. Anodes of the light emitting diodes L1 through Ln are connected to respective ends of normally opened switching elements SL1 through SLn which have the other ends connected in common to the emitter of a driving transistor Q. Including these switching elements SL1 through SLn, a first switching circuit 1 is formed. The collectors of the photo transistors PT1 through PTn are connected to respective ends of normally opened switching elements S1 through Sn which have the other ends connected in common to a waveform shaper 2. Including these switching elements S1 through Sn, a second switching circuit 3 is formed.
A start signal Sc is applied to the driving transistor Q and a counter circuit 4 from a host computer (not shown). The counter circuit 4 starts its counting motion in response to the start signal Sc to produce a pulse signal P on every count and supply a count data Dc. The pulse signal P is applied to the first and second switching circuits 1 and 3 so that a decoder or other means (not shown) sequentially, correspondingly closes respective pairs of switching elements S1 and SL1, S2 and S12, et seq. to the final ones Sn and SLn so as to sequentially activate the light emitting diodes L1 through Ln to produce light signals. The driving transistor Q having received the start signal Sc is now conductive. The photo transistors PT1 through PTn are sequentially made conductive by light reception from associated light emitting diodes L1 through Ln unless a light signal is blocked by a finger or other object, but they are maintained nonconductive if the light signal thereto is blocked. The waveform shaper 2 produces a waveform as shown in FIG. 12(a), depending on conduction or nonconduction of the photo transistors PT1 through PT2. The waveform of FIG. 12(a) is produced with light signals from the light emitting diodes L5 and L(m+6) are blocked.
The output of the waveform shaper 2 is amplified by an amplifier 5 and subsequently applied to a comparator 6. The comparator 6 also receives the pulse signal P from the counter circuit 4, and produces a memory signal Sm if it does not receive the output from the waveform shaper 2 at the moment when the pulse signal P is entered therein. FIG. 12(b) shows a waveform produced by the comparator 6 in which the memory signal Sm is outputted at "5" in the X axis and "m+6" in the Y axis.
The memory signal Sm is applied to a memory 7 which responsively stores the count data Dc from the counter circuit 4. The count data Dc is further applied to an output controller 8 which calculates a proper coordinate from the count data Dc and supplies a corresponding coordinate signal to the host computer.
A third form of the prior art optical coordinate system input device is explained hereinbelow, referring to FIG. 13. A number of light emitting diodes L1 through Ln are placed on two adjacent margins of the front face outer periphery of a CRT or other image display apparatus. Photo transistors PT1 through PTn employed as the light receptor elements are placed on the other two adjacent margins and individually opposed to the light emitting diodes L1 through Ln. Horizontally opposed pairs of light emitting diodes (L1 through Lm) and photo transistors (PT1 through PTm) form X axes of the coordinate system, and vertically opposed pairs of light emitting diodes (Lm+1 through Ln) and photo resistors (PTm+1 through PTn) form Y axes of the coordinate system. Cathodes of the light emitting diodes L1 through Ln and emitters of the photo resistors PT1 through PTn are all connected to ground. Anodes of the light emitting diodes L1 through Ln are connected to respective ends of normally opened switching elements SL1 through SLn which have the other ends connected in common to the emitter of a driving transistor Q1. Including these switching elements SL1 through SLn, a first switching circuit 1 is formed. Collectors of the photo transistors PT1 through PTn are connected to respective ends of normally opened switching elements S1 through Sn which have the other ends connected in common to a waveform shaper 2. Including these switching elements S1 through Sn, a second switching circuit 3 is formed. The collector of the driving transistor Q1 is connected to a driving power source V. The light emitting diodes L1 through Ln, first and second switching circuits 1 and 3, waveform shaper 2 and driving transistor Q1 form a coordinate system detector.
The waveform shaper 2 is arranged as explained hereinbelow. The other ends of the switching elements S1 through Sn are connected together, and their junction is further connected to the base of a transistor Q2 via a capacitor C1. The emitter of the transistor Q2 is connected to ground, and the collector thereof is connected to the driving power source V via series-connected resistors R1 and R2. The base of the transistor Q2 is connected to the driving power source V via a resistor R3. The junction of the resistors R1 and R2 is connected to a common junction of the other ends of the switching elements S1 through Sn. The collector of the transistor Q2 is connected to an amplifier 4a via a capacitor C2. When one of the photo transistors PT1 through PTn decreases in impedance on reception of a light signal, the voltage at the common junction of the other ends of the switching elements S1 through Sn drops. The drop of the output terminal voltage is inverted and amplified in the transistor Q2, and a pulse output is applied to the amplifier 4a.
A start signal Sc is applied to the driving transistor Q1 and a counter circuit 5a from a host computer (not shown). The counter circuit 5a starts its counting motion in response to the start signal Sc to supply a pulse signal P to the first and second switching circuits 1 and 3 and a comparator 6 on every count and to supply a count data Dc to a memory 7. The first and second switching circuits 1 and 3 are activated in response to the pulse signal P so that a decoder or other means (not shown) correspondingly closes respective pairs of switching elements S1 and SL1, S2 and S12, et seq. to the final ones Sn and SLn so as to sequentially activate the light emitting diodes L1 through Ln to produce light signals. The driving transistor Q1 having received the start signal Sc is now conductive. The photo transistors PT1 through PTn decrease in impedance and hence in output terminal voltage due to reception of light signals from opposed light emitting diodes L1 through Ln unless the light signals are blocked by a finger or other object. A pulse output is supplied from the waveform shaper 2 to the amplifier 4a. When the light signals are blocked and cannot reach the photo transistors PT1 through PTn, no pulse output is applied to the amplifier 4a from the waveform shaper 2. The output of the waveform shaper 2 is amplified in the amplifier 4 and applied to the comparator 6 for comparison with the pulse signal P from the counter circuit 5a. If the comparator 6 does not receive the pulse output from the amplifier 4a at the moment when the pulse signal P is entered, it applies a memory signal Sm to the memory 7 which responsively stores the count data Dc from the counter circuit 5a. The count data Dc is further applied to an output controller 8 which calculates a proper coordinate from the count data Dc and supplies a corresponding coordinate signal to the host computer.
A fourth form of the prior art optical coordinate system input device is explained hereinbelow, referring to FIG. 14.
A number of light emitting diodes L1 through Ln are placed on two adjacent margins of the front face outer periphery of a CRT or other image display apparatus. Photo transistors PT1 through PTn employed as the light receptor elements are placed on the other two adjacent margins and opposed to the light emitting diodes L1 and Ln. Horizontally opposed pairs of light emitting diodes (L1 through Lm) and photo transistors (PT1 through PTm) form X axes of the coordinate system, and vertically opposed pairs of light emitting diodes (Lm+1 through Ln) and photo resistors (PTm+1 through PTn) form Y axes of the coordinate system. Cathodes of the light emitting diodes L1 through Ln and emitters of the photo resistors PT1 through PTn are all connected to ground. Anodes of the light emitting diodes L1 through Ln are connected to respective ends of normally opened switching elements SL1 through SLn which have the other ends connected in common to the emitter of a driving transistor Q1. Including these switching elements SL1 through SLn, a first switching circuit 1 is formed. The collectors of the photo transistors PT1 through PTn are connected to respective ends of normally opened switching elements S1 through Sn which have the other ends connected in common to a waveform shaper 2. Including these switching elements S1 through Sn, a second switching circuit 3 is formed. The collector of the driving transistor Q1 is connected to a driving power source V. The light emitting diodes L1 through Ln, first and second switching circuits 1 and 3, waveform shaper 2 and driving transistor Q1 form a coordinate system detector.
The waveform shaper 2 is arranged as explained hereinbelow. The other ends of the switching elements S1 through Sn are connected together, and their junction is further connected to the base of a transistor Q2 via a capacitor C1. The emitter of the transistor Q2 is connected to ground, and the collector thereof is connected to the driving power source V via series-connected resistors R1 and R2. The base of the transistor Q2 is connected to the driving power source V via a resistor R3. The junction of the resistors R1 and R2 is connected to a common junction of the other ends of the switching elements S1 through Sn. The collector of the transistor Q2 is connected to an amplifier 4a via a capacitor C2. When one of the photo transistors PT1 through PTn decreases in impedance on reception of a light signal, the voltage at the common junction of the other ends of the switching elements S1 through Sn drops. The drop of the output terminal voltage is inverted and amplified in the transistor Q2, and a pulse output is applied to the amplifier 4a.
A start signal Sc is applied to the driving transistor Q1 and a counter circuit 5a from a host computer (not shown). The counter circuit 5a starts its counting in response to the start signal Sc to supply a pulse signal P to the first and second switching circuits 1 and 3 and a comparator 6 on every count and to supply a count data Dc to a memory 7. The first and second switching circuits 1 and 3 are activated in response to the pulse signal P so that a decoder or other means (not shown) sequentially, correspondingly closes respective pairs of switching elements S1 and SL1, S2 and S12, et seq. to the final ones Sn and SLn so as to sequentially activate the light emitting diodes L1 through Ln to produce light signals. The driving transistor Q1 having received the start signal Sc is now conductive. The photo transistors PT1 through PTn decrease in impedance and hence in output terminal voltage due to reception of light signals from associated light emitting diodes L1 through Ln unless the light signals are blocked by a finger or other object, so that a pulse output is supplied from the waveform shaper 2 to the amplifier 4a. When the light signals are blocked and cannot reach the photo transistors PT1 through PTn, no pulse output is applied to the amplifier 4a from the waveform shaper 2. The output of the waveform shaper 2 is amplified in the amplifier 4a and applied to the comparator 6 for comparison with the pulse signal P from the counter circuit 5a. If the comparator 6 does not receive the pulse output from the amplifier 4a at the moment when the pulse signal P is entered, it applies a memory signal Sm to the memory 7 which responsively stores the count data Dc from the counter circuit 5a. The count data Dc is further applied to an output controller 8 which calculates a proper coordinate from the count data Dc and supplies a corresponding coordinate signal to the host computer.
A fifth form of the prior art optical coordinate system input device is explained hereinbelow, referring to FIG. 15.
A number of light emitting diodes L1 through Ln are placed on two adjacent margins of the front face outer periphery of a CRT or other image display apparatus. Photo transistors PT1 through PTn employed as the light receptor elements are placed on the other two adjacent margins and opposed to the light emitting diodes L1 and Ln. Horizontally opposed pairs of light emitting diodes (L1 through Lm) and photo transistors (PT1 through PTm) form X axes of the coordinate system, and vertically opposed pairs of light emitting diodes (Lm+1 through Ln) and photo resistors (PTm+1 through PTn) form Y axes of the coordinate system. Cathodes of the light emitting diodes L1 through Ln and emitters of the photo resistors PT1 through PTn are all connected to ground. Anodes of the light emitting diodes L1 through Ln are connected to respective ends of normally opened switching elements SL1 through SLn which have the other ends connected in common to the emitter of a driving transistor Q1. Including these switching elements SL1 through SLn, a first switching circuit 1 is formed. The collectors of the photo transistors PT1 through PTn are connected to respective ends of normally opened switching elements S1 through Sn which have the other ends connected in common to a waveform shaper 2. Including these switching elements S1 through Sn, a second switching circuit 3 is formed. The collector of the driving transistor Q1 is connected to a driving power source V. The light emitting diodes L1 through Ln, first and second switching circuits 1 and 3, waveform shaper 2 and driving transistor Q1 form a coordinate system detector.
When a central operational processing unit (CPU) supplies a switching signal a in response to an instruction supplied from a host computer (not shown), the first and second switching circuits 1 and 3 sequentially, correspondingly close respective pairs of switching elements S1 and SL1, S2 and S12, et seq. to final ones Sn to SLn. The driving transistor Q1 having received a driving signal b from the CPU 4' at the base thereof is now conductive. The driving signal b may be a series of several pulses supplied from the CPU while the pairs of switching elements S1 through Sn and SL1 through SLn are sequentially closed. When one of the photo transistors PT1 through PTn receives a light signal from associated one of the selectively driven photo diodes L1 through Ln, the wave form shaper 2 produces a pulse signal. If the selected one of the photo transistors PT1 through PTn cannot receive the light signal due to a positional instruction by a finger or other blocker, the waveform shaper does not produce a pulse signal. The signal from the waveform shaper 2 is amplified in an amplifier 5' and applied to the CPU 4' which obtains therefrom the positional signal input by a finger or other means.